Automatic verification of control logics in safety instrumented system design for chemical process industry |
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| Authors: | Jinkyung Kim Il Moon |
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| Institution: | 1. Collaborative Research Center for Energy Engineering, Institute of Industrial Science, The University of Tokyo, 4-6-1 Komaba, Meguro-ku, Tokyo 153-8505, Japan;2. Solution Research Laboratory, Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo 152-8550, Japan;3. Department of Chemical Engineering, Tokyo University of Agriculture and Technology, 2-24-16 Nakacho, Koganei-shi, Tokyo 184-8588, Japan;1. Key Laboratory of Industrial Internet of Things & Networked Control, Ministry of Education, Chongqing University of Posts and Telecommunications, Chongqing 400065, PR China;2. College of Automation, Chongqing University, Chongqing 400044, PR China |
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| Abstract: | Automatic model checking is used to determine the error-free design of the SIS (Safety Instrumented System) and to find the logical errors in the chemical processes. It proposes an automatic technique to provide and to modify the P&ID design of SIS control logics. This method can be applied to verify its correctness of SIS and to find the logical errors by synthesizing a feasible sequence automatically. This study focuses on automatic verifying and synthesizing for the design, operability and reachability of SIS control logics in chemical processes. |
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